module SRAM#(
    parameter ADDR_LENGTH = 64,
    parameter DATA_WIDTH  = 8,
    parameter ADDR_WIDTH  = $clog2(ADDR_LENGTH)
)(
    input clk,
    input rst_n,

    input [ADDR_WIDTH-1:0]addr,
    input write,
    //input read,
    input [DATA_WIDTH-1:0]data_in,
    output [DATA_WIDTH-1:0]data_out
);

    reg [DATA_WIDTH-1:0] mem[0:ADDR_LENGTH-1];
    reg [ADDR_WIDTH-1:0] addr_r;

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            addr_r <= 'd0;
        else
            addr_r <= addr;
    end

    assign data_out = mem[addr_r];

    always @(posedge clk or negedge rst_n) begin
        if(write)
            mem[addr] <= data_in;
    end

endmodule